(1) Field of the Invention
The present invention relates to semiconductor devices in general, and in particular, to a method of reducing polysilicon depletion in MOS transistors.
(2) Description of the Related Art
One of the detrimental effects of the present drive to obtain ever smaller geometries in semiconductor devices is the degradation of the conductivity of polysilicon gate electrodes which are important in determining the performance of such devices. This is because, as the width of the gate electrode is reduced or shrunk, the conductivity of the gate electrode also tends to be reduced, which in turn, tends to reduce the efficiency of the gate electrode by way of impacting the speed and other aspects of the device. In addition, the reduction in the amount of dopant activated in a low thermal budget process tends to cause carrier depletion at the interface between the gate electrode and the gate dielectric. This situation additionally effects the ability of the device to perform. It is disclosed later in the embodiments of the present invention a method of reducing dopant depletion in polysilicon gates in order to regain the performance as it would be present in the larger and unshrunk devices. It will be apparent then to those skilled in the art that the fact that the later disclosed method is applicable to both complementary MOS (CMOS) logic devices as well as the memory devices makes the method that more advantageous to the art of making semiconductor devices in general.
A conventional method of forming gate electrodes in a metal-oxide semiconductor (MOS) memory device is shown in FIGS. 1a-1f. However, it will be understood by the skilled that conventional CMOS methods may have just as well been cited here for purposes of illustrating the forming of gate electrodes. Thus, in FIG. 1a, layer of gate oxide (30) is thermally grown over substrate (10) using conventional methods. Next, a first polysilicon layer (40) is formed followed by the deposition of nitride layer (50). A photoresist layer (60) is then spun over the substrate and then patterned with a floating gate pattern as shown in FIG. 1b, which in turn, is etched into the nitride layer (50) as shown in FIG. 1c. The polysilicon layer is then doped through ion implantation (65), followed by a conventional anneal step (not shown) to activate the dopants. Normally, the anneal step is insufficient to drive the implanted impurities down the entire depth of polysilicon layer (40). This is called the xe2x80x9cpoly depletion effectxe2x80x9d which results in poor control of the threshold voltage, and for which a remedy is disclosed later in the embodiments of the present invention. Subsequently, photoresist layer (60), which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (45) as shown in FIG. 1d. Subsequently, the nitride layer is removed where now polyoxide (45) serves as a hard mask to remove all the first polysilicon portions except those that are covered by the polyoxide (FIG. 1e). The control gate is formed by depositing second polysilicon layer (80) over intergate layer (70), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate.
As integrated circuit geometries shrink, the relationships between the individual elements of the circuits also lend to change. Thus, the gate electrodes of a device such as shown in FIG. 1f are preferably spaced at reduced distances one from the other, in support of the overall reduced device geometry. However, the reduced distances between adjacent polysilicon gates tends to make them more difficult to fabricate. One reason for this is that one gate electrode over a complementary device may be oppositely doped in relation to another gate electrode over an adjoining complementary device. Before patterning the gate electrode layer, the reduced distance between the oppositely doped regions of the gate electrode layer tends to allow the dopans to diffuse into the adjoining regions. This tends to reduce or even destroy the intended effect of the dopants in the gate electrode regions, resulting in a degradation of the integrated circuit.
In related art, Puchner, et al., of U.S. Pat. No. 6,090,651 address the problems cited above, and disclose a method of forming depletion free polysilicon electrodes by first forming a supersaturated layer on a semiconductor CMOS device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer. The liquefied initial phase layer is cooled to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer. An initial phase layer of either polysilicon or amorphous silicon may then be deposited over the CMOS device. After laser annealing, the initial phase layer is transformed into a doped polysilicon gate electrode that can be patterned and further processed.
Nakajima, et al., in U.S. Pat. No. 6,001,714 disclose a different method of manufacturing a polysilicon thin film transistor (TFT). With this method, a dopant is implanted into a polysilicon thin film formed on an substrate with a gate having a tapered edge which is used as a mask to form a source and a drain. An energy beam then slantingly irradiates from the side of the edge of the gate to the surface of the substrate. Thus, the source and drain are activated and, at the same time, the energy beam exposes the polysilicon thin film below the edge of the gate to activate the channel region implanted the dopant.
Still another method is disclosed by Talwar, et al., in U.S. Pat. No. 5,908,307 for fabricating field effect transistors (FET) with reduced dimensions. Here, a given surface layer of crystalline silicon is first amorphized to a given depth. Thereafter a given amount of doping material is deposited as a film on the surface of the given amorphized surface layer of the silicon. Then, a portion of the given amorphized surface layer of the silicon is temporarily heated for a certain time to a temperature which is sufficient to melt amorphized silicon but is insufficient to melt crystalline silicon (since the melting temperature of amorphized silicon is substantially below that of crystalline silicon). After a predetermined heating time, the melted silicon of the heated portion is permitted to cool, thereby effecting a recrystallization of the silicon of this portion of the given surface layer. The layer is then patterned and further processed.
Janning of U.S. Pat. No. 4,619,034 discloses a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. The method comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride there beneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO2. According to Janing, doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation. The recrystallized silicon is patterned into the device active area and a source and drain in alignment with the underlying gate are implanted therein.
Levinstein, et al., on the other hand, show, in U.S. Pat. No. 4,555,842, a method directed to the fabrication of a VLSI CMOS device of the type that comprises complementary-threshold-voltage NMOS and PMOS transistors which include silicide-on-doped polysilicon gates. The method comprises forming a polysilicon layer on a substrate, selectively introducing dopants into specified regions of the layer, forming a cap layer on the doped polysilicon layer, and heating the device with the cap layer in place to lock dopants in lattice sites in the specified regions of the polysilicon layer.
The present invention discloses a different method of forming polysilicon gates, or electrodes, where dopant depletion at the interface near the gate dielectric layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to the melt depth. In this manner, poly depletion effect is greatly reduced and hence performance of the device improved. The disclosed method is applicable to both n+ doped polysilicon gates (NMOS) and p+doped polysilicon gates (PMOS), as well as to the floating gate and control gates of memory devices.
It is therefore an object of the present invention to provide method of forming a polysilicon electrode with reduced dopant depletion effect.
It is another object of this invention to provide a method of utilizing laser annealing to reduce poly depletion in MOS transistors.
It is yet another object of the present invention to provide a method of utilizing laser annealing to reduce poly depletion in both the floating and control gates of memory devices.
It is still another object of this invention to provide a method of pre-amorphizing a polycrystalline layer prior to ion implantation to a desired depth such that during laser annealing, these dopants will diffuse uniformly to a desired melt depth.
It is an overall object of the present invention to provide a method of forming poly electrodes in transistors and memory devices where the desired threshold voltage is obtained and the effects of deep submicron shrinkage is mitigated in favor of regained dopant depth through a judicious laser annealing subsequent to ion implantation of the electrodes.
These objects are accomplished by providing a substrate; forming a pad oxide layer over said substrate; forming a nitride layer over said pad oxide layer; patterning said nitride layer to form a trench over said pad oxide layer; removing said pad oxide layer and exposing said substrate at the bottom of said trench; optionally forming and removing a sacrificial layer; forming a gate oxide layer over said substrate at the bottom of said trench; forming a polysilicon layer over said substrate, including within said trench; performing chemical mechanical polishing (CMP) to remove excess polysilicon over said trench; etching said polysilicon layer in said trench to a desired thickness; in-situ amorphizing upper portion of said polysilicon layer by implanting ions into said polysilicon layer to form an amorphous (xcex1-Si) layer over said polysilicon layer; doping said polysilicon layer by implanting ions; performing laser irradiation of selected wavelength and fluence to melt and regrow said xcex1-Si layer while at the same time driving said ions deeply into said polysilicon electrode reaching but adjacent said underlying oxide layer; and continuing the completion of said MOS transistor by depositing another material (e.g., metal) into the trench, followed by CMP, for making contact.